Enhanced Error Coding Scheme

An enhanced FEC system is proposed and described. The scheme has been simulated with both Single carrier and Multi-carrier (OFDM) Modulation. Purpose This proposal is offered as a basis for FEC in the 802.16.3 PHY layer. Notice This document has been prepared to assist IEEE 802.16. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. 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The contributor also acknowledges and accepts that this contribution may be made public by IEEE 802.16. 2000-10-30 IEEE 802.16.1c-00/45 2 Patent Policy and Procedures The contributor is familiar with the IEEE 802.16 Patent Policy and Procedures (Version 1.0) , including the statement “IEEE standards may include the known use of patent(s), including patent applications, if there is technical justification in the opinion of the standards-developing committee and provided the IEEE receives assurance from the patent holder that it will license applicants under reasonable terms and conditions for the purpose of implementing the standard.” Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chair as early as possible, in written or electronic form, of any patents (granted or under application) that may cover technology that is under consideration by or has been approved by IEEE 802.16. The Chair will disclose this notification via the IEEE 802.16 web site . 2000-10-30 IEEE 802.16.1c-00/45 3 Enhanced Error Coding Scheme Peter Close, Keith Pickavance, Sean Sonander, Dave Williams Advanced Hardware Architectures, Inc. 1. Turbo Product Codes Introduction The following is offered to provide additional insights into Turbo Product Codes (also known as Block Turbo Codes) as well as to provide a summary of subsequent sections of this document. • Generic Turbo Product Codes architectures for encoder and decoders are non-proprietary and can be supported by various suppliers who may or may not choose to use proprietary decoder algorithms. The use of product codes was described in published literature in 1954 [1] and the use of iterative decoding techniques for these codes were described in published papers and at least one textbook [2] in the early 1980’s. • For high code rates (R>0.7) Turbo Product Codes are capable of outperforming other known FEC coding schemes. • Turbo Product Codes simulations have been verified with actual hardware that has been verified by independent third parties. It has been shown that simulations match hardware performance within normal measurement accuracy. • In addition to both software simulations and hardware verification, a union-bound based analysis for AWGN channels and QPSK modulation has been generated, which supports the simulation and hardware results [5]. This analysis can be used to predict code performance to arbitrarily low BER’s. The accuracy of these predictions has been verified with actual hardware measurements for selected codes down to approximately 10 11 . • Encoder complexities for Turbo Product Codes are low (in the range of 10K gates), are non-proprietary and are constructed from Hamming and/or parity codes. Memory requirements are low and in the region of 500 1Kbits. Latency through such an encoder is less than a few bit periods at the highest data rates. • Decoder complexities for Turbo Product Codes are higher than for Reed-Solomon based concatenated codes. This increase is offset by the increased performance available or can be traded off against reduced complexity in other system level components such as lower power amplifier requirements, smaller antennas, higher receiver noise figures, etc. The increase in complexity is estimated to be less than 5% of the total system complexity. 2000-10-30 IEEE 802.16.1c-00/45 4 Turbo Code Description The Block Turbo Code is a Turbo decoded Product Code (TPC). The idea of this coding scheme is to use wellknown product codes in a matrix form for two-dimensional coding, or in a cubical form for three dimensions. The matrix form of the two-dimensional code is depicted in Figure 1. The kx information bits in the rows are encoded into nx bits, by using a binary block (nx,kx) code. The binary block codes employed are one error correcting BCH-codes (Bose-Chaudhuri-Hocquenghem), or Hamming Codes. The redundancy of the code is rx = nx kx and dx is the Hamming distance. After encoding the rows, the columns are encoded using another block code (ny,ky), where the check bits of the first code are also encoded. The overall block size of such a product code is n = nx × ny, the total number of information bits k = kx × ky and the code rate is R = Rx × Ry, where R i = ki/ni, i=x, y. The Hamming distance of the product code is d = dx × dy. checks on checks checks checks k2